[研究] 大象

看板NTUGIEE_EDA作者moonshade (翻滾吧！貓咪)時間19年前 (2005/05/28 20:00)推噓8(9推 1噓 1→)

留言11則, 6人參與討論串1/2 (看更多)

In this paper, the authors propose a placement technique for circuit rows multi-voltage designs, in which rows of different voltage supplies can be interwove and level converting filp-flops are placed across two rows with different voltage supplies. The technique first runs Gordian algorithm to get an initial solution. Based on the solution, it assigns the voltage supply of each row by the majority voltage supply of cells on the row. Then they propose an ILP algorithm to redistribute every cell not compatible to the voltage supply of the row it's currently on, to the nearest row with compatible voltage supply. The experiments are based on ISCA98 benchmark, shows the increment of wirelength is 20% in average. 1. Though the topic is interesting, the proposed technique is not new. The ILP based legalizing method is a well-known technique, and is considered time consuming especially for large scale designs. 2. Therefore, the reviewers think the authors should report the runtimes of the experiments and try the algorithm on the larger benchmarks, such as ISPD-02 IBM benchmark. 3. The wirelength increment is too large, which is 20% in average. The reviewers think that this issue should be considered in global placement stage, or the wirlength increment of this algorithm is not considered efficient. 4. The “interleaves” at the second paragraph of section 2 should be “interweaves”. -- 1980以前的paper看起來都像用打字機打的，然後圖是用糨糊黏上去的，那個時代的人應該想不到今天電腦的能耐，那麼，十年後的科技會是什麼樣子呢? -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 140.112.48.60 ※ 編輯: moonshade 來自: 140.112.48.60 (05/28 20:09) ※ 編輯: moonshade 來自: 140.112.48.60 (05/28 20:10) ※ 編輯: moonshade 來自: 140.112.48.60 (05/28 20:10)

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internal

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yellowfishie

218.164.38.150 05/28, , 2^F

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yellowfishie

218.164.38.150 05/28, , 3^F

218.164.38.150 05/28, 3^F